Discussion on Computer Engineering +

Computer Engineering + (Math)
Attached below are three documents containing all the questions for the assignment.Answer all questions. (send the answers in 3 different word documents, each for every document attached)

COE 202, Term 201
Digital Logic Design
Assignment# 3
Due date: Saturday, Nov. 28, 2020
Q.1. You are required to design and implement an ALU with the following ports:  A and B are inputs, and are n-bit signed numbers represented in 2’s complement  F is 3-bit unsigned number for ALU function selector  R is the signed ALU result represented in 2’s complement. You will have to determine the minimum number of bits required for R such that an overflow never occurs. Below is a table of ALU functions along with an illustration of its port interface
Function Code ALU Result
F=000 R=(A+B)/4
F=001 R=4*(A+B)
F=010 R=2*A + B
F=011 R=A – 2*B
F=100 R=A and B
F=101 R= not(A)
F=110 R=A or B
F=111 R=A xor B
a) (5 points) Determine the size of R in bits such that overflow can never occur.
b) (10 points) Show the implementation of the ALU using MSI components and the minimum number of additional gates. Hint: you will have to use some form of extension (zero- or sign-extension).
c) (10 points) Create behavioral Verilog modules for every MSI component you used in Part (b). Make sure the size of every module you design is parameterized, so that you can change your design easily during the testing phase.
d) (5 points) Create a structural model for your ALU designed in Part (b) using the modules you derived in Part (c).
e) (5 points) Write a Verilog test bench that tests your ALU module in Part (d) assuming that A and B are 4-bits using the following input values:
A B F Expected output
4 4 0 R=2
2 1 1 R=12
-1 -5 2 R=-7
-1 -5 3 R=+9
-1 -2 4 R=-2
-1 -2 5 R=0
-1 -2 6 R=-1
-1 -2 7 R=+1 Allow a period of 20 ps between two consecutive test cases.
f) (5 points) Write a single behavioral Verilog module that models the given ALU.
g) (5 points) Write a Verilog test bench to test your behavioral ALU model in Part (f). Assuming that A and B are 4-bit, use the following input values:
A B F Expected output
4 4 0 R=2
2 1 1 R=12
-1 -5 2 R=-7
-1 -5 3 R=+9
-1 -2 4 R=-2
-1 -2 5 R=0
-1 -2 6 R=-1
-1 -2 7 R=+1 Allow a period of 20 ps between two consecutive test cases.
h) (5 points) Submit a report (Word or PDF document) that should contain: i. Problem description ii. Your answers to Parts (a) and (b) iii. All the behavioral models derived in Part (c), structural model in Part (d), and the test bench in Part (e) iv. The behavioral model in Part (f) and its test bench in Part (g) v. The timing diagrams (waveforms) taken directly as snapshots from the simulator. Have as many snapshots as needed to cover all the test cases. The assignment can be solved individually, or in groups of two students. Submit a soft copy of your solution on Blackboard in a zip file including your Verilog models.

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